Technical Field
This invention relates generally to the field of semiconductors and, more particularly, to approaches for forming a through silicon via (TSV) device having low stress thin film gaps.
Related Art
During fabrication, testing, and service, packages with through silicon via (TSV) structures may undergo temperature excursion. When the operational temperature is higher than the stress-free temperature, expansion of metal within a via will induce tensile stresses (e.g., in circumferential directions) in silicon interposers due to a mismatch of coefficients of thermal expansion such that the tensile stresses could result in transistors being “squeezed” or “stretched” by adjacent TSVs resulting in performance drift. Moreover, such stresses may result in micro-cracks within the silicon dioxide (SiO2) and silicon to initiate and damage the silicon interposer by radial cracking.